XA304

Dual Port Gigabit Ethernet Transcode Application

General Description

The Xelic XA304 Application supports the mapping of dual Transcoded Gigabit Ethernet signals into ODU0 frames and ODTU01 multiplexing for ODU1/OTU1 frame rate transport. As shown in the block diagram below, the XA304 application contains two Gigabit Ethernet Transcoder/OPU0 Mappers (XCO0M), two ODU0 Framers (XCO0) with GMP processing, an ODTU01 Multiplexer (XCO01MX) and an ODU1/OTU1 Framer (XCO1). Independent XA304 Transmit and Receive Data Path Processors are used and share a 16-bit generic register interface to provide internal memory mapped access for configuration and performance monitoring. A client side Gigabit Ethernet clock is used for 8B/10B processing of incoming Gigabit Ethernet signals. The remaining XA304 Transmit Processor data path operates off a common ODU1 or OTU1 rate clock using a data valid scheme. Likewise, a client side Gigabit Ethernet clock is used for 8B/10B processing of generated Gigabit Ethernet signals. The remaining XA304 Receive Processor data path uses a common ODU1 or OTU1 rate clock with a data valid scheme. This application has been verified through extensive simulation testing and hardware validated on Xelic evaluation platforms using industry standard test equipment. The XA304 application can be extended to include the mapping of several other client signals into ODU0 frames including SONET/SDH STS-3, STS-12, Video, 1 Gigabit Fibre Channel, etc. The GMP processor for each ODU0 framer can be configured to process any rate that will fit into an OPU0 container.

Features

    General

    • Implements 16-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.
    • Supports transmit and receive facility and terminal loopback configurations.

    Mapper (2xGigabit Ethernet Transcode + 2xODU0 Framer + ODTU01MX + ODU1/OTU1 Framer)

    • Accepts two client side 1000 BASE-X Gigabit Ethernet signals and performs transcoding into GFP frames.
    • Inserts ODU0 frame alignment signal information with a programmable corruption option.
    • Flexible insertion and extraction of ODU, and OPU overhead byte information.
    • Supports corruption capability through internal register programming for debug or test purposes.
    • Provides optional scrambling (1 + x + x3 + x12 + x16) with polynomial corruption capability for diagnostics.
    • Inserts OTU SM, GCC0, and RES overhead through internal register control or an external overhead port.
    • Inserts ODU RES, TCM ACT, FTFL, PM, EXP, GCC1, GCC2, and APS/PCC overhead through internal register control or an external overhead port.
    • Provides 6 levels of tandem connection overhead insertion.
    • Programmable positive (1x and 2x) and negative (1x and 2x) justification counters provided for asynchronous 1000 BASE-X payload types with user defined interval or errored second accumulation.
    • Optionally inserts ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals.
    • Provides 2 independent ODU0 signals or a single ODU01 multiplexed ODU1 frame format at the line side interface.
    • ODUTU01 multiplexer performs OPU1 tributary timeslot interleaving and mapping of 2 ODU0 frames into an ODU1 signal.

    Demapper (ODU1/OTU1 Framer + ODTU01MX + 2xODU0 Framer + 2xGigabit Ethernet Transdecode)

    • Accepts optional line side ODU1 or OTU1 frame formats.
    • Performs ODU0 frame alignment with programmable OOF/OOM and LOF/LOM detection.
    • Detects FAS OOF, LOF, LOA, OOM, LOM, and LOMA conditions with optional interrupt generation.
    • Provides saturating counters with programmable latch and clear or incoming error sync capture configurations.
    • Provides independent performance counters for the accumulation of OOF and OOM errors with optional interrupt generation for OOF and OOM error detection.
    • Interprets and extracts OTU SM, GCC0 and RES overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Interprets and extracts ODU RES, TCM ACT, TCM (support for up to 6 levels of tandem connection monitoring), PM, EXP, GCC1, GCC2, and APS/PCC overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Provides independent performance counters for the accumulation BIP-8, and BEI errors (SM, TCMi, PM), with optional interrupt generation.
    • Provides Transdecoding of two independent 1000 BASE-X Gigabit Ethernet signals encapsulated in transparent GFP frames received from ODU0 framers and performs rate adaptation through idle insertion and removal at the client side interface.