Gigabit Ethernet Transcoder/OPU0 Mapper

General Description

The Xelic OPU0 Mapper Core (XCO0M) performs Gigabit Ethernet Transcoding for OPU0 mapping applications.

Incoming Gigabit ethernet data is synchronously mapped into 75 octet Transparent GFP frames for OTN ODU0 payload transport. XCO0M Transmit and Receive Processors support the mapping and demapping of Gigabit Ethernet client data including performance monitoring with GFP Client Signal Fail (CSF) insertion and detection.

Line side data is transferred through a transmit data valid and receive data valid scheme using an 8-bit data bus operating at a clock rate up to 170MHz.

The XCO0M Transmit Processor performs timing transparent transcoding of incoming Gigabit Ethernet data streams. Gigabit Ethernet alignment and 8B/10B decoding is performed in addition to performance monitoring functions. Decoded Gigabit Ethernet data is then encapsulated in Transparent Mode GFP frames, each with a single 64B/65B superblock, and made available for OPU0 transport. During a detected signal fail condition, the incoming Gigabit Ethernet stream can either be replaced with a link fault indicator as specified in IEEE 802.3 or can be replaced by a programmable GFP CSF as specified in the G.7041 standard.

The XCO0M Receive Processor accepts Transparent Mode GFP frames and extracts payload data for processing.

The GFP processor provides user control of core header descrambling and payload descrambling. Single bit payload header errors are corrected (optional) to provide more reliable transport of client packet information. Independent counters are available to monitor the accumulation of SSF errors, core header corrected frames, payload header corrected frames, payload header uncorrected frames, client data packets, and client invalid packets. An interrupt and interrupt mask register is provided to allow users the ability to ignore various conditions that may be detected.

Gigabit Ethernet data is extracted from Transparent Mode GFP frames and stored in an internal FIFO as 8B data.

FIFO 8B data is delivered to the system side interface after 8B/10B signal encoding is performed. If a signal fail condition is detected, the 8B/10B encoder can be programmed to generate 10B_ERR, K30.7, or link fault indication signals.

The XCO0M implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between transmit and receive processors with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.



    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCO0M is available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.
    • Implements clock valid scheme for variable data flow applications.

    Transmit 8B/10B Decoder

    • Supports Gigabit Ethernet Transcoding for ODU0 payload transport.
    • Provides alignment of incoming data and decodes 10B data into 8B characters.
    • Optionally generates link fault indication for signal fault detection
    • Supports incoming error monitoring with optional K30.7 or 10B_ERR character insertion.
    • Includes performance counters and maskable interrupts for incoming disparity error detection, invalid character detection, and loss of synchronization detection.
    • Test modes are provided to force K30.7 error characters in addition to LOS and LSYNC conditions.

    Transmit GFP Processor

    • Provides test mode for generation of user specified client data or client management frame types.
    • Supports insertion of programmable CSF signals for LOS or LSYNC conditions.
    • Generates 75 octet transparent GFP data streams with a single superblock configuration.
    • Transparent mode GFP suppresses the use of GFP idle frames or 65B_PAD character insertions.