XCO3M

40 Gigabit Ethernet PCS/Transcoder OPU3 Mapper

General Description

The Xelic 40 Gigabit Ethernet PCS/Transcoder OPU3 Mapper Core (XCO3M) performs Block Alignment, Lane Alignment/Deskew, PCS performance monitoring, and Ethernet 40GBASE-R signal transcoding for OTN OPU3 payload mapping applications. In addition, an optional XLGMII interface is provided for Media Access Control (MAC) communication. The XCO3M contains independent PCS Decode/Transcode and PCS Encode/Transdecode Processors with lane alignment and deskew support. Ethernet 40GBASE-R data is transferred using four 66 bit lanes (CFP interface) operating at 156.25MHz. Transcoded/Transdecoded data is transferred to/from an OTN network element using a 256 bit bus operating at an ODU3 rate of 157.50 MHz or an OTU3 rate of 168.04MHz.

The XCO3M PCS Decode/Transcode Processor contains a PCS (64B/66B) Block Align and Deskew Block, PCS Performance Monitoring Block, Transcoder Block, and XLGMII Interface Block. The PCS Block Align and Deskew Block performs 64B/66B block alignment, lane alignment, and lane deskew with high BER monitoring and BIP error detection for each of the four incoming lanes (CFP Interface) as outlined in IEEE 802.3ba specifications. The PCS performance monitoring Block contains an optional descramble function, local and remote fault detection and insertion, interrupts for various detected conditions, and idle test pattern insertion/detection as described in the IEEE 802.3ba specification. The Transcoder Block performs 513B code block transcoding with framing and flag bit protection through 1027B code blocks (Transcoding Mode) as outlined in the G.709 specification. The XLGMII interface Block allows for support of direct connection to Media Access Control (MAC) devices. Incoming alignment markers are removed when XLGMII mode of operation is enabled. Counters are provided for the accumulation of PCS sync errors (BER), PCS Block Errors, and lane marker PCS BIP3 parity errors for all four lanes.

The XCO3M PCS Encode/Transdecode Processor contains a Transdecode Block, Performance Monitoring Block, PCS Align Marker Insert Block, and XLGMII Interface Block. The Transdecode Block performs 1027B block alignment and 513B code block transdecoding with framing and flag bit interpretation as outlined in the G.709 specification. In addition, 1027B sync errors are detected and an optional 1027B descramble option is provided. The Performance Monitoring Block detects 1027B OTN BIP errors and provides interrupts for various detected conditions. PCS performance monitoring is provided with an optional scramble function, local and remote fault detection and insertion, and idle test pattern insertion/detection. The PCS Align Marker Insert Block monitors lane alignment and detects skew violations with optional support for lane PCS BIP3 parity adjustments though 1027B parity information provided from the Transdecode Block. During a detected signal fail condition, incoming data can optionally be replaced with link fault ordered set information. The XLGMII interface Block allows for support of direct connection to Media Access Control (MAC) devices. Alignment markers are generated as specified in IEEE 802.3ba when XLGMII mode of operation is enabled. Counters are provided for the accumulation of 1027 sync errors (BER), PCS Block Errors, and OTN BIP parity errors for all four lanes.

The XCO3M implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between PCS Decode/Transcode and PCS Encode/Transdecode processors with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCO3M is available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.

    PCS Decode/Transcode Processor

    • Supports Transcoding or XLGMII modes of operation.
    • Provides alignment of incoming PCS blocks for all four incoming lanes.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Contains optional PCS descrambling and 1027B scrambling functions.
    • Performs lane marker alignment and deskew.
    • Includes performance counters and maskable interrupts for PCS sync errors (BER), PCS Block errors, and lane marker PCS BIP3 error detection.
    • A test mode is provided for the insertion and detection of PCS idles.
    • Contains an optional set of RMON counters.

    PCS Encode/Transdecode Processor

    • Supports Transdecoding or XLGMII modes of operation.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Contains optional PCS scrambling and 1027B descrambling functions.
    • Supports monitoring of lane skew and provides PCS BIP3 adjustment capability.
    • Includes performance counters and maskable interrupts for 1027B sync errors (BER), PCS Block errors, and lane OTN BIP error detection.
    • A test mode is provided for the insertion and detection of PCS idles.
    • Contains an optional set of RMON counters.