100G OTN Frame/Lane Alignment Unit Core

General Description

The Xelic 100G Optical Transport Network (OTN) Frame/Lane Alignment Unit Core (XCO4AU) performs OTL Frame Alignment, Lane Alignment, Lane Deskew, and Lane Rotation, as outlined in G.709 and G.798 specifications with optional scramble and descramble functionality. Incoming high speed data from optics is timed using recovered clocks and transferred to system clock timing with a data valid scheme for downstream processing. A flexible data bus architecture is used to provide 80 byte transfers for FPGA applications and 40/48 byte transfers for ASIC implementations.

The XCO4AU Transmit Processor contains a Transmit Controller, Scrambler, OTU4 AIS Generator and Lane Rotation block for multichannel parallel interface support. The Transmit Controller uses incoming FAS signaling to enable optional OTU4 signal scrambling. The core internally generates a 5-bit logical lane marker (LLM) ranging 0 19 used for Lane Rotation and inserts the LLM over the 3rd OA2 byte. The OTU4 AIS generator is enabled to insert framed OTL AIS signaling as specified in G.709 and G.798 standards for OTL4.10 configurations. OTU4 frames are distributed after lane rotation over twenty logical lanes (ten physical lanes after bit-interleaving) with minimal skew.

The XCO4AU Receive Processor contains an Optical channel Transport Lane (OTL) Frame Aligner, OTL AIS detector, Lane Aligner with Deskew and Lane Rotation, and OTN frame descrambler. The OTL Frame Aligner performs frame alignment of OTU4 frames with configuration options for OOF and LOF algorithm state transitions. The OTL AIS detector monitors incoming lanes for OTL AIS and reports status through internal maskable interrupts. Following frame alignment, incoming lanes are aligned and lane deskew is performed before lane data is multiplexed (lane rotation) into OTU4 frames. A receive system side clock is used to retime incoming data to a system reference.

The XCO4AU provides Transmit Processor terminal loopback, Transmit Processor facility loopback, Receive Processor facility loopback, and Receive Processor facility loopback modes of operation for system debug purposes.

A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.



    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCO4AU core available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.
    • Implements 16-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.
    • Provides transmit and receive loopback options for diagnostic purposes.
    • Operation for 100G OTN transport.


    • Provides optional framed OTU4 AIS and OTL AIS insertion.
    • Optionally scrambles (1 + x + x3 + x12 + x16) incoming OTU4 signals.
    • Supports OTU4 lane rotation for OTL4.10 multichannel parallel interfacing.


    • Performs OTUk frame alignment with programmable OOF/OOM/OOR and LOF/LOFLANE/LOR/LOL detection.
    • Supports OPSMnk_TT functions for OTL 4.10 interface (frame alignment, lane recovery, lane deskew, 16 byte block mux).
    • Detects LOS, LOF, LOM, LOFLANE, LOL, LOR, OOF, OOM, OOR conditions with maskable interrupt generation.
    • Detects OTL AIS and OTUk-AIS error condition with maskable interrupt generation.
    • Supports Alignment and deskew of incoming lane data.
    • Provides Receive Processor system clock transfer capability.
    • Supports optional descrambling (1 + x + x3 + x12 + x16) of incoming OTU4 signals.
    • Provides block multiplexing (lane rotation) of incoming OTL4.10 signals into OTU4 frames