XCO4M

100 Gigabit Ethernet Mapper

General Description

The Xelic 100 Gigabit Ethernet OPU4 Mapper Core (XCO4M) performs Block Alignment, Lane Alignment/Deskew, and PCS performance monitoring, for OTN OPU4 payload mapping applications. In addition, an optional CGMII interface is provided for Media Access Control (MAC) communication. The XCO4M contains independent PCS Mapper and PCS Demapper with lane alignment and deskew support. Ethernet 100GBASE-R data is transferred using ten 66 bit lanes (CFP interface) operating at 156.25MHz. Mapped Ethernet data is transferred to/from an OTN network element using a 640 bit bus operating at an ODU4 clock rate of 163.74 MHz or an OTU4 clock rate of 174.70MHz.

The XCO4M PCS Mapper contains a PCS (64B/66B) Block Align and Lane Deskew Block, PCS Performance Monitoring Block, and optional CGMII Interface Block. The PCS Block Align and Lane Deskew Block performs 64B/66B block alignment, lane alignment, and lane deskew with high BER monitoring and BIP error detection for each of the incoming lanes (CFP Interface) as outlined in IEEE 802.3ba specifications. Incoming 10 physical lane data is demultiplexed into 20internal lanes (i.e.: each internal lane is associated with a PCS Lane, and is derived from either the odd or the even bits of one of the incoming physical lanes) for internal processing. The PCS performance monitoring Block contains a descramble function, local and remote fault detection and insertion, interrupts for various detected conditions, and idle test pattern insertion/detection as described in the IEEE 802.3ba specification. The optional CGMII Interface Block allows for support of direct connection to Media Access Control (MAC) devices. Incoming alignment markers are removed when CGMII mode of operation is enabled. Counters are provided for the accumulation of PCS sync errors (High BER), PCS Block Errors, and lane marker PCS BIP3 parity errors for all lanes.

The XCO4M PCS Demapper contains a Performance Monitoring Block, PCS Align Marker Insert Block, and optional CGMII Interface Block. The Performance Monitoring Block provides interrupts for various detected conditions. PCS performance monitoring is provided with a scramble function, local and remote fault detection and insertion, and idle test pattern insertion/detection. The PCS Align Marker Insert Block monitors lane alignment and detects skew violations. During a detected signal fail condition, incoming data can optionally be replaced with link fault ordered set information. The 20 PCS lanes are bit-multiplexed onto the outgoing 10 physical lane data bus. The optional CGMII Interface Block allows for support of direct connection to Media Access Control (MAC) devices. Alignment markers are generated as specified in IEEE 802.3ba when CGMII mode of operation is enabled. Counters are provided for the accumulation of PCS Block Errors for all lanes.

The XCO4M implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between PCS Mapper and PCS Demapper with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCO4M is available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.

    PCS Mapper

    • Supports 100GBASE-R Mapping or optional CGMII modes of operation.
    • Provides alignment of incoming PCS blocks for all twenty incoming lanes.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Performs lane marker alignment and deskew.
    • Includes performance counters and maskable interrupts for PCS sync errors (high BER), PCS Block errors, and lane marker PCS BIP3 error detection, recalculated BIP3/BIP7 overwrite option.
    • A test mode is provided for the insertion and detection of PCS idles.

    PCS Demapper

    • Supports 100GBASE-R Demapping or optional CGMII modes of operation.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Supports monitoring of lane skew and provides PCS BIP3 error detection, recalculated BIP3/BIP7 overwrite option.
    • Includes performance counters and maskable interrupts for PCS Block error detection.
    • A test mode is provided for the insertion and detection of PCS idles.