XCO4ML

100G Ethernet Mapper for use with Xilinx CMAC

General Description

The Xelic 100 Gigabit Ethernet OPU4 Mapper Core (XCO4ML) cooperates with the Xilinx CMAC to perform Block Alignment, Lane Alignment/Deskew, and PCS performance monitoring, for OTN OPU4 payload mapping applications. The XCO4ML contains independent PCS Mapper and PCS Demapper functionality with lane alignment and deskew support. Support is provided for applications requiring Ethernet 100GBASE-R data transfers using 4 80-bit lanes (CAUI4). Mapped Ethernet data is transferred to/from an OTN network element using a 320 bit bus operating at an ODU4 or OTU4 clock rate.

The XCO4ML PCS Mapper utilizes the Xilinx Ultrascale+ Devices Integrated 100G Ethernet Subsystem (CMAC) for PCS (64B/66B) Block Alignment and Lane Deskew with high BER monitoring and BIP error detection for each of the incoming lanes. The PCS performance monitoring Block contains a descramble function, local and remote fault detection and insertion, interrupts for various detected conditions, and idle test pattern insertion/detection as described in the IEEE 802.3ba specification. Counters are provided for the accumulation of PCS sync header errors (High BER), PCS Block Errors, and lane marker PCS BIP3 parity errors for all lanes.

The XCO4ML PCS Demapper contains a Performance Monitoring Block and a PCS Align Marker Insert Block. The Performance Monitoring Block provides interrupts for various detected conditions. PCS performance monitoring is provided with a scramble function, local and remote fault detection and insertion, and idle test pattern insertion/detection. The PCS Align Marker Insert Block monitors lane alignment and detects skew violations. During a detected signal fail condition, incoming data can optionally be replaced with link fault ordered set information. The 20 PCS lanes are bit-multiplexed onto the outgoing physical lane data bus. Counters are provided for the accumulation of PCS Block Errors for all lanes.

The XCO4ML implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between PCS Mapper and PCS Demapper with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

    General

    • Suitable for Xilinx Ultrascale+ FPGA implementations.
    • Integration support and maintenance available.
    • XCO4ML is available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.

    PCS Mapper

    • Supports 100GBASE-R Mapping mode of operation.
    • Cooperates with Xilinx CMAC to perform the following functions:
    • oProvides alignment of incoming PCS blocks for all twenty incoming lanes.
    • oPerforms lane marker alignment and deskew.
    • oA test mode is provided for the insertion and detection of PCS idles.
    • oProvides RMON statistics for accumulation.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Includes performance counters and maskable interrupts for PCS sync errors (high BER), PCS Block errors, and lane marker PCS BIP3 error detection, recalculated BIP3/BIP7 overwrite option.
    • Contains an optional set of RMON counters.

    PCS Demapper

    • Supports 100GBASE-R Demapping mode of operation.
    • Cooperates with Xilinx CMAC to perform the following functions:
    • oProvides RMON statistics for accumulation.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Provides PCS BIP3 error detection, recalculated BIP3/BIP7 overwrite option.
    • Includes performance counters and maskable interrupts for PCS Block error detection.
    • A test mode is provided for the insertion and detection of PCS idles.
    • Contains an optional set of RMON counters.