XCO5Flex

OTN 400G Flex Framer

General Description

The Xelic Optical Transport Network (OTN) 400G Flex Framer Core (XCO5Flex) performs Optical Channel Transport Unit (OTU), Optical Channel Data Unit (ODU), and Optical Channel Payload Unit (OPU) overhead/data processing, aligns incoming ODUFlex frames, and provides overhead interpretation with error detection and performance monitoring. The XCO5Flex contains independent transmit and receive processors with external ports for overhead insertion and extraction with support for ODU5Flex BMP payload mapping mode of operation. Delay Measurement capability is provided in the Transmit (PM/TCMi) processor. Client and Line side data transfers use read enable and data valid signaling at clock rates up to 350 MHz to allow for flexible system clocking schemes.

The XCO5Flex Transmit Processor inserts OTUk, ODUk, and OPUk overhead, calculates and inserts parity and automatically generates Backward Defect Indication (BDI) signaling. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM), Path Monitoring (PM), and Tandem Connection Monitoring (TCMi) overhead insertion. The XCO5Flex supports up to 6 levels of tandem connection overhead insertion and interpretation. Diagnostics support includes optional corruption of inserted parity and maintenance signal insertion. Programmable payload support includes bit synchronous, null test, and PRBS mapping types.

The XCO5Flex Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOFLOM algorithm state transitions. Incoming ODUFlex frames aligned for OTN overhead processing. OTUk, ODUk, and OPUk overhead information is extracted to both internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, OOM, and LOFLOM. ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. OPUk payload type mismatch error conditions are detected.

Performance counters (configurable for error sync mode) are provided for the accumulation of detected (XCO5Flex Receive Processor) BIP-8 parity and BEI errors for OTU SM, ODU TCMi, and ODU PM. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.

The XCO5Flex provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.

A 32-bit generic register interface for access and configuration of internal memory mapped locations is included.

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCO5Flex core available under flexible single use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.
    • Provides for payload request modes of operation.
    • Implements 32-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.
    • Supports transmit and receive facility and terminal loopback configurations.

    Transmit

    • Provides programmable PM/TCMi Delay Measurement capability.
    • Flexible insertion of OTUk, ODUk, and OPUk overhead byte information.
    • Inserts ODUFlex frame alignment signal information.
    • Inserts OTUk SM, GCC0, and RES overhead through internal register control or an external overhead port.
    • Inserts ODUk RES, TCM ACT, FTFL, PM, EXP, GCC1, GCC2, and APS/PCC overhead through internal register control or an external overhead port.
    • Provides 6 levels of tandem connection overhead insertion.
    • Optionally inserts ODU AIS, ODU LCK, ODU OCI, and client generic AIS maintenance signals.

    Receive

    • Performs ODUFlex frame alignment with programmable OOF/OOM and LOFLOM detection.
    • Detects FAS OOF, OOM, and LOFLOM conditions with optional interrupt generation.
    • Provides saturating counters with programmable latch and clear or incoming error sync capture configurations.
    • Provides independent performance counters for the accumulation of OOF and OOM errors with optional interrupt generation for OOF and OOM error detection.
    • Interprets and extracts OTUk SM, GCC0 and RES overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Interprets and extracts ODUk RES, TCM ACT, TCM (support for up to 6 levels of tandem connection monitoring), PM, EXP, GCC1, GCC2, and APS/PCC overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Provides independent performance counters for the accumulation BIP-8 and BEI errors (SM, TCMi, PM) with optional interrupt generation.