XCO5M

400Gb/s Ethernet Mapper with RMON

General Description

The Xelic 400 Gigabit Ethernet OPU Mapper Core (XCO5M) performs PCS fault monitoring/insertion, RMON binning, RC Block insertion/extraction, optional pause-frame insertion (de-map direction), and the scramble/descramble function required to map/demap 400GE into an ODUflex payload. The XCO5M contains independent PCS Mapper and PCS Demapper blocks. This core is instantiated between the XCO5BSFEC and the XCO5FLEX. The datapath input and output to this core is a simple 66b PCS stream. The client side interface that connects to the XCO5BSFEC is 1320-bits wide (66*20) and the line-side interface that connects to the XCO5FLEX is 1280-bits wide (64*20). The data on the client interface will always be aligned such that a 66-bit PCS block will align to the top of the bus. Both interfaces are clocked by an overclocked system clock with push through data-valid signaling. This core is expected to operate at a clock rate between 332.1MHz and 360MHz.

The XCO5M implements a generic register interface for access and configuration of internal memory mapped register locations. This interface is shared between PCS Mapper and PCS Demapper with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • XCO5M core available under flexible single use licensing terms with netlist or source code deliverables.
    • Integration support and maintenance available.
    • Implements 32-bit register interface for programming of internal registers.
    • Provides transmit and receive loopback options for diagnostic purposes.

    Mapper

    • Includes nominal timing input port.
    • Provides block alignment check of incoming PCS blocks.
    • Support rate compensation block insertion.
    • Provides local fault, remote fault, and ordered set generation/detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Includes performance counters for PCS Error Blocks.
    • A test mode is provided for the insertion and detection of PCS idles.
    • Contains an optional set of RMON counters.
    • Includes Precision Timing Protocl (PTP) interface.

    Demapper

    • Provides full block alignment for incoming PCS blocks.
    • Supports rate compensation block removal.
    • Provides local fault, remote fault, and ordered set generation/detection.
    • Supports incoming error monitoring with optional error block insertion.
    • Includes performance counters for PCS Error Blocks.
    • A test mode is provided for the insertion and detection of PCS idles.
    • Contains an optional set of RMON counters.
    • Includes Precision Timing Protocl (PTP) interface.
    • Optional 66b interface port.
    • Optional Pause Frame generation.