XCOC124MAP

100G/200G/400G Timesliced OTN FLEXE Mapper

General Description

The Xelic Optical Transport Network (OTN) Time Sliced Mapper Core (XCOC124MAP) performs Mapper/Demapper functions and OPUk overhead processing for 100G, 200G and 400G client signal rates that combined provide a throughput up to 400Gb/s. The XCOC124MAP supports dynamic time-slice reconfiguration without interruption to existing provisioned traffic. The XCOC124MAP contains independent Transmit and Receive processors with time-sliced external ports for overhead insertion and extraction. Client and Line side data transfers use data valid signaling at clock rates up to 411 MHz to allow for flexible system clocking schemes. A flexible data bus architecture is used for ODUk transport to provide bit transfers for FPGA and ASIC implementations.

The XCOC124MAP Transmit Processor accepts client data streams with a configurable push or pull interface and maps the client data to an OPUk payload. GMP/BGMP mapping data is accepted from an external port. OPUk overhead information is inserted into ODUk frames based on the client mapping strategy used.

The XCOC124MAP Receive Processor contains a frame alignment unit for all provisioned time slices. Incoming ODUk frames are aligned for OTN time-sliced overhead processing. OPUk overhead information is extracted to both time-sliced internal register locations and an external port. Client data is demapped from the OPUk payload based on the client mapping strategy used.

The XCOC124MAP provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.

A 32-bit generic register interface for access and configuration of internal memory mapped locations is included

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCOC124MAP core available under flexible single-use licensing terms with netlist or source code deliverables.
    • Implements flexible data bus architecture.
    • Implements 32-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.
    • Supports transmit facility, transmit terminal, receive facility, and receive terminal loopback configurations.

    Transmit

    • Accepts client signal bit streams for GMP, BGMP, or BMP OPUk payload mapping.
    • Client interface can be configured as push or pull depending on the latency and fifo requirements.
    • Provides external GMP interface for explicit control of GMP/BGMP Cm and CnD values.
    • Provides register controls for adjusting Cm values.

    Receive

    • Demaps client signal bit streams for GMP, BGMP, or BMP OPUk payload mapping.
    • Extracts and interprets OPUk overhead to monitor state of GMP/BGMP mapping.
    • Provides external GMP interface for output of received GMP/BGMP Cm and CnD values.