XCOC24BSFEC

200Gb/s, 400Gb/s IEEE 8012.BS FEC Core

General Description

The Xelic 2x200G/400G RS-FEC over CDAUI-16 Interface (XCOC24BSFEC) core performs encoding and decoding using RS(544,514) codewords as specified in the IEEE 802.3bs standard. The XCOC24BSFEC contains independent encoder and decoder functions fully compliant with the IEEE 802.3bs specification. Line and client side data is transferred at 200GBASE_R PHY or 400GBASE-R PHY rate, respectively using a 640-bit or a 1280-bit data bus operating at a nominal frequency of 355 MHz. In 200G mode, either one or two 200GBASE_R PHY can be used.

The XCOC24BSFEC encoder contains a 64B/66B to 256B/257B transcoder that constructs a 257-bit block from a group of four 66-bit blocks. The 257-bit blocks are then scrambled before alignment markers get inserted in the data stream. The RS(544, 514) encoding is then applied and the RS encoded data is distributed to 16 FEC lanes, one 10-bit symbol at a time in a round robin distribution starting with the lowest numbered FEC lane.

The XCOC24BSFEC decoder contains a block Alignment Lock, Lane De-skew and Lane Reorder block, RS decoder and a 256B/257B to 64B/66B transcoder block. Alignment lock within a lane is achieved when two consecutive alignment markers have been identified within the expected period. Once the alignment lock has been achieved for all 16 lanes, the lanes are de-skewed. After the lanes have been de-skewed and re-ordered, the lanes are considered to be FEC aligned. Once aligned, the RS decoder can correct any correctable symbol errors ( 15 symbol errors). Corrected symbol and bit (optional) error counts are provided on a logical lane basis. Corrected codewords and uncorrectable codewords are also available. The 256B/257B to 64B/66B transcoder block then extracts a group of four 66-bit blocks from each 257-bit block.

Features

  • Suitable for ASIC implementations.
  • Integration support and maintenance available.
  • XCOC24BSFEC core available under flexible single use licensing terms with netlist or source code deliverables.
  • Complies with the IEEE 802.3bs specification.
  • Programmable between 2x200G and 1x400G mode.
  • In 200G mode, either one or two 200G PCS are supported.
  • Encoder includes single bit error insertion for diagnostic purposes.
  • Degraded SER indication to remote host.
  • Provides corrected codeword, and uncorrected codeword outputs.
  • Provides outputs for line values of corrected symbols by 25G Logical Lane
  • Provides outputs for line values of corrected ones and corrected zeroes by 25G Logical Lane (optional)