XCOCN

B100G OTN Framer

General Description

The Xelic Optical Transport Network (OTN) Beyond 100G Framer Core (XCOCn) performs Optical Channel Transport Unit (OTU), Optical Channel Data Unit (ODU), and Optical Channel Payload Unit (OPU) overhead/data processing, aligns incoming OTU4 or ODUCn frames, and provides overhead interpretation with error detection and performance monitoring. The XCOCn contains independent transmit and receive processors with external ports for overhead insertion and extraction with support for ODUCn streaming and payload mapping modes of operation. Delay Measurement capability is provided in the transmit processor (PM). Client and Line side data transfers use read enable and data valid signaling at clock rates up to 355 MHz to allow for flexible system clocking schemes.

The XCOCn Transmit Processor inserts OTUCn, ODUCn, and OPUCn overhead, calculates and inserts parity, and automatically generates Backward Defect Indication (BDI) signaling. Support is provided for generic mapping procedure (GMP) justifications. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM) and Path Monitoring (PM) overhead insertion. Diagnostics support includes optional corruption of inserted parity and maintenance signal insertion. Programmable payload support includes GMP, null test, and PRBS mapping types.

The XCOCn Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOFLOM algorithm state transitions. Incoming OTUCn or ODUCn frames are aligned for OTN overhead processing. OTUCn, ODUCn, and OPUCn overhead information is extracted to both internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, OOM, and LOFLOM. Support is provided for generic mapping procedure (GMP) justifications. ODUCn AIS and client payload PRBS patterns are detected with optional interrupt generation. OPUCn payload type mismatch error conditions are detected and support is provided for programmable payload type accept and inconsistent thresholds.

Performance counters (configurable for error sync mode) are provided for the accumulation of detected (XCOCn receive processor) BIP-8 parity and BEI errors for OTUCn SM and ODUCn PM. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.

The XCOCn provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.

The XCOCn implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between transmit and receive processors with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

    General

    • Suitable for FPGA and/or ASIC implementations.
    • Integration support and maintenance available.
    • XCOCn core available under flexible single use licensing terms with netlist or source code deliverables.
    • Provides for streaming and payload request modes of operation.
    • Implements 32-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.
    • Supports transmit and receive facility and terminal loopback configurations.
    • Support is provided for generic mapping procedure (GMP) justifications.
    • Support is provided for hitless adjustment of ODUflex (HAO).

    Transmit

    • Accepts streaming ODUCn frames or mapped client signals bit streams.
    • Provides programmable PM Delay Measurement capability.
    • Flexible insertion of OTUCn, ODUCn, and OPUCn overhead byte information.
    • Inserts OTUCn or ODUCn frame alignment signal information.
    • Inserts OTUCn SM and GCC0 overhead through internal register control or an external overhead port.
    • Inserts ODUCn PM, EXP, GCC1, GCC2, and APS/PCC overhead through internal register control or an external overhead port.
    • Optionally inserts ODUCn AIS maintenance signals and PRBS test payload signals.

    Receive

    • Provides programmable PM Delay Measurement capability.
    • Performs selectable OTUCn or ODUCn frame alignment with programmable OMFI OOM and LOM detection.
    • Detects changes in FAS and MFAS conditions with optional interrupt generation.
    • Provides saturating counters with programmable latch and clear or incoming error sync capture configurations.
    • Interprets and extracts OTUCn SM and GCC0 overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Interprets and extracts ODUCn PM, EXP, GCC1, GCC2, and APS/PCC overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
    • Provides independent performance counters for the accumulation BIP-8 and BEI errors (SM, PM) with optional interrupt generation.