XCO23EFEC4
40G/4x10G G975.1 I.4 Enhanced FEC Core
General Description
The Xelic XCO23EFEC4 I.4 Enhanced Forward Error Correction (EFEC) Core performs FEC encoding and decoding for either 1 OTU3 or 4 independent OTU2 streams. The XCO23EFEC4 contains independent encoder and decoder functions with interleaved BCH and Reed Solomon algorithms. The XCO23EFEC4 is compliant with the G975.1.I.4 specification. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz. This core can be used in place of 1 40G core and 4 10G cores and is a fraction of the size.
Features
- Optimized for ASIC implementations.
- Integration support and maintenance available.
- XCO23EFEC4 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.4 specification.
- Encoder includes single bit error insertion for diagnostic purposes.
- Decoder includes four iterative stages of error correction, BCH1 – RS1 – BCH2 – RS2.
- Each decode stage can be disabled under via input control signals.
- Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
- Provides uncorrected codeword outputs.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Provides a single-bit error insertion capability.
- Overall latency of 16us for 40G ports, 40us for 10G ports.
Applications
- OTU2, OTU3 line cards
- Test equipment
Please contact for additional information.