XCO2EFEC4
10G G975.1 I.4 Enhanced FEC Core
| Document | Size | Download |
|---|---|---|
| Product Brief | 33.62 KB |  |
| Fact Sheet | 50.22 KB | |
| Data Sheet | 130.28 KB | |
General Description
The Xelic 10Gb/s I.4 Enhanced Forward Error Correction (EFEC) Core (XCO2EFEC4) generates codeword parity bits and performs error detection and correction for OTN OTU2 frames. The XCO2EFEC4 contains independent encoder and decoder functions with interleaved BCH and Reed Solomon algorithms. The XCO2EFEC4 is compliant with the G975.1.I.4 specification and has been through extensive interoperability testing. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU2 rate using a 64-bit data bus operating at 167.33MHz.
Features
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO2EFEC4 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.4 specification.
- Encoder includes single bit error insertion for diagnostic purposes.
- Decoder includes four iterative stages of error correction, BCH1 – RS1 – BCH2 – RS2.
- Each decode stage can be disabled via input control signals.
- Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
- Provides uncorrected codeword outputs.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Provides a single-bit error insertion capability
- Overall latency of 61us.
Applications
- OTN/SONET add/drop multiplexers
- OTN switch
- Digital cross connects
- OTN and/or SONET/SDH line cards
- Test equipment
Please contact for additional information.