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XCO2M
10G Multiprotocol Mapper Core

Document Size Download
Product Brief29.13 KBDownload PDF
Fact Sheet83.25 KBDownload PDF
Data Sheet815.31 KBDownload PDF

General Description

The Xelic 10Gb/s Multi-Protocol Mapper Core (XCO2M) contains configurable client signal processors with integrated Frame Mapped/Transparent Mode GFP support to provide flexible OTN payload transport capability. XCO2M Transmit and Receive Processors support the mapping and demapping of 8 Gigabit Fibre Channel, CBR data, or 10 Gigabit Ethernet (G.Sup43.6.2 and G.Sup43.7.3) client data streams for standard or nonstandard ODU-2 frame payloads. Line side data is transferred through a transmit data request and receive data valid scheme using a 64-bit data bus operating at a clock rate up to 167.33MHz.

The XCO2M Transmit Processor performs 8B/10B decoding for incoming 8 Gigabit Fibre Channel data streams, maps XGMII 10 Gigabit ethernet data into Ethernet PDU with Preamble and Ethernet Ordered Sets (PP/OS encoding), processes 10 Gigabit ethernet packets, and supports Frame Mapped/Transparent Mode GFP payload data encapsulation. Incoming 8GB Fibre Channel data is optionally received in 8B/10B format and decoded or in 8B data format with the internal 8B/10B decoder disabled. Decoded Fibre Channel data is then encapsulated in Transparent Mode GFP frames adapted to the incoming line data rate. Incoming 10 Gigabit Ethernet frames are received in either packet (G.Sup43.6.2) format for immediate encapsulation into Frame Mapped GFP frames or XGMII format where 10GB ethernet data and ordered sets are mapped (GSup43.7.3) prior to Frame Mapped GFP frame encapsulation.

The XCO2M Receive Processor accepts Frame Mapped/Transparent Mode GFP frames and extracts payload data for processing. Client 8 Gigabit Fibre Channel data is extracted from Transparent Mode GFP frames and stored in an internal FIFO as 8B data. FIFO 8B data can be read directly (internal 8B/10B encoder disabled) through the system side interface or delivered after encoding as an 8B/10B signal. Client 10 Gigabit ethernet data is extracted from Frame Mapped GFP frames and delivered in XGMII data format after Ethernet PDU and Ethernet Ordered Set Decoding (GSup43.7.3) or extracted directly from Frame Mapped GFP frames as packets (G.Sup43.6.2).

The Frame Mapped/Transparent Mode GFP processor supports both client data and client management frame types. Client management frames can be inserted through either the system interface (10 Gigabit Ethernet Packet Mode only) or through internal register programming. In addition, client management frames can be inserted at programmable intervals or forced upon user request. GFP control frames are generated to allow for GFP frame rate adaptation in the absence of available client information ready for transport. The GFP processor provides user control of core header scrambling/descrambling, FCS insertion/extraction, payload scrambling/descrambling, and payload header GFP type field programming. Single bit payload header errors are corrected (optional) to provide more reliable transport of client packet information.

Independent counters are available to monitor the accumulation of SSF errors, FCS errors, core header corrected frames, payload header corrected frames, payload header uncorrected frames, control frames, client management packets, client data packets, and client invalid packets. An interrupt and interrupt mask register is provided to allow users the ability to ignore various conditions that may be detected.

The XCO2M implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between transmit and receive processors with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.

Features

  • Suitable for FPGA and/or ASIC implementations.
  • Integration support and maintenance available.
  • XCO2M is available under flexible single use licensing terms with netlist or source code deliverables.
  • Implements flexible data bus architecture.
  • Implements clock valid scheme for variable data flow applications.
  • Compliant with ITU G.Sup43 Specifications.
  • Provides alignment of incoming data and decodes 10B data into 8B characters.
  • Supports incoming error monitoring with optional K30.7 or 10B_ERR character insertion.
  • Identifies 10G Ethernet PDU with Preamble and Ethernet Ordered Sets for GFP-F frame encapsulation.
  • Provides test mode for generation of user specified client data or client management frame types.
  • Supports both frame mapped and transparent modes of operation.
  • Supports pad character insertion for SOP error conditions when configured for 10 Gigabit Ethernet Packet mode.
  • Supports control frame (idle) insertion for GFP frame rate adaptation Optional GFP frame payload type field configuration through external pins or internal register programming Supports error monitoring with optional K30.7 mapping of incoming 10B_ERR characters detected.
  • Performs rate adaptation through the insertion of idles.
  • Supports system side XGMII interface.

Applications

  • Traffic Manager
  • DWDM and WDM systems
  • OTN/SONET add/drop multiplexers
  • Digital cross connects
  • OTN and/or SONET/SDH line cards
  • Test equipment

Please contact for additional information.