40G/4x10G G975.1 I.4 Enhanced FEC Core

General Description

The XCO23EFEC4 is an ITU-T G.975.1 Appendix I.4 compliant Super FEC Encoder, Decoder pair consisting of 2 interleaved codes: RS(1023, 1007, 8) parent outer code, and BCH(2047, 1959, 8) parent inner code.

This ITU-T G709 I.4 compliant scheme provides a higher coding gain than the standard RS(255, 239) for gaussian error distributions while maintaining the standard 7 (16:239) parity:data overhead.

This core can be programmed for 4x10G, 40G OTU3 or 40G OTL3.4 operation and is intended for use with one XCO3 40G Digital Wrapper OTN Framer Core or with four XCO2 10G Digital Wrapper OTN Framer Core.

In 4x10G mode, the XCO23EFEC4 codec can process 4 channels of ODU2 and each channel is programmed to be 32-bit wide and operates at a rate of OTU2/32. The XCO23EFEC4 decoder performs bit correction in each individual channel and provides the statistical counts for each channel.

In 40G mode, The XCO23EFEC4 codec can process 1 channel of ODU3 and the channel is programmed to be 128-bit wide and operates at a rate of OTU3/128. The XCO23EFEC4 decoder performs bit correction and provides the statistical counts for both OTU3 data steam as well as OTL3.4 or Bit Position Modulo N operation.


  • Suitable for FPGA and/or ASIC implementations.
  • Integration support and maintenance available.
  • XCO23EFEC4 core available under flexible single use licensing terms with netlist or source code deliverables.
  • Complies with ITU-T G.975.1 Amendment I.4 specification.
  • Decoder includes four iterative stages of error correction, BCH1 RS1 BCH2 RS2.
  • Each data stream can be disabled under via input control signals.
  • Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
  • Provides uncorrected codeword outputs.
  • Architecture facilitates RAM sharing with other FEC cores.
  • Provides a configurable High BER alarm.
  • Overall latency of X us.