40G G975.1 I.4 Enhanced FEC Core

General Description

The Xelic native 40Gb/s I.4 Enhanced Forward Error Correction (EFEC) Core (XCO3EFEC4) generates codeword parity bits and performs error detection and correction for OTN OTU3 frames. The XCO3EFEC4 contains independent encoder and decoder functions with interleaved BCH and Reed Solomon algorithms. The XCO3EFEC4 is compliant with the G975.1.I.4 specification. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz.


  • Suitable for FPGA and/or ASIC implementations.
  • Integration support and maintenance available.
  • XCO3EFEC4 core available under flexible single use licensing terms with netlist or source code deliverables.
  • Complies with ITU-T G.975.1 Amendment I.4 specification.
  • Encoder includes single bit error insertion for diagnostic purposes.
  • Decoder includes four iterative stages of error correction, BCH1 RS1 BCH2 RS2.
  • Each decode stage can be disabled via input control signals.
  • Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
  • Provides uncorrected codeword outputs.
  • Architecture facilitates RAM sharing with other EFEC cores.
  • Provides a configurable High BER alarm.
  • Provides a single-bit error insertion capability
  • Overall latency of 16us.


  • OTN/SONET add/drop multiplexer
  • OTN switch
  • Digital cross connects
  • OTN and/or SONET/SDH line cards
  • Test equipment