40G G975.1 I.7 Enhanced FEC Core

General Description

The Xelic 40Gb/s I.7 Enhanced Forward Error Correction (EFEC) Core (XCO3EFEC7) generates codeword parity bits and performs error detection and correction for OTU3 data streams. The XCO3EFEC7 contains independent encoder and decoder functions which utilize two orthogonally concatenated BCH codes, providing a standard 7 percent parity overhead solution. The XCO3EFEC7 implements the G975.1.I.7 specification and has been through extensive interoperability testing with other implementations. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz.


  • Optimized for ASIC implementations.
  • Integration support and maintenance available.
  • Core available under flexible single use licensing terms with netlist or source code deliverables.
  • Complies with ITU-T G.975.1 Amendment I.7 specification.
  • Standard 7 percent parity overhead.
  • Encoder includes single bit error insertion for diagnostic purposes.
  • Decoder includes five iterative stages of BCH error correction, Row1 – Col1 – Row2 – Col2 – Row3.
  • Each decode stage can be disabled via input control signals.
  • Provides corrected ones and corrected zeroes outputs.
  • Provides uncorrected codeword outputs.
  • Provides status outputs for internal MSYNC state machine.
  • Architecture facilitates RAM sharing with other EFEC cores.
  • Provides a configurable High BER alarm.
  • Overall latency of 35us.


  • OTU3 line cards
  • Test equipment