XS701 40G OTN Transponder

General Description

The Xelic 40G Optical Transport Network (OTN) Transponder provides the flexible transport of signals through a configurable highly integrated subsystem. A 40GE client signal is supported with line side ODU3/OTU3 and ODU3e2/OTU3e2 signals configurable through internal register control. The subsystem contains independent 40G OTN Framer, OTL3.4, 40GE, and 40G GFEC core processors with configurable options and a comprehensive programmable feature set. Independent interfaces are provided for framer GMP payload insertion/extraction control and external overhead port insertion/extraction. Optional loopbacks bypass modes, counters, and programmable consequential actions are available for debug and system integration purposes. A flexible 256-bit architecture is implemented with a data valid scheme and a high speed system clock operating at a rate up to 185MHz. The 40G Optical Transport Network (OTN) Transponder subsystem is targeted for both ASIC and FPGA applications.



    • Implements 16-bit register interface for programming of internal registers.
    • Complies with ITU-T G.709 and ITU-T G.798 specifications.

    40G Ethernet Processing

    • Supports Transcoding/Transdecoding operations.
    • Provides alignment of incoming PCS blocks for all four incoming lanes.
    • Optionally generates link fault indication for signal fault detection.
    • Supports incoming performance monitoring with optional error block insertion.
    • Contains optional PCS descrambling and 1027B scrambling functions.
    • Performs lane marker alignment and deskew.

    40G GFEC

    • Contains 7 parity overhead
    • Encoder includes single bit error insertion for diagnostic purposes.
    • Provides outputs for scrambled line values of corrected ones and corrected zeroes
    • Provides corrected symbols and uncorrected codewords outputs.
    • Provides a configurable High BER alarm.
    • Overall latency of less than 1us.


    • Provides optional OTUk AIS insertion.
    • Supports OTU3 lane rotation for OTL3.4 multichannel parallel interfacing.
    • Detects FAS OOF/OOM and LOF/LOL conditions with optional interrupt generation.
    • Detects OTL AIS and OTUk-AIS error condition with optional interrupt generation.
    • Supports Alignment and deskew of incoming lane data.
    • Provides inverse multiplexing (lane rotation) of incoming OTL3.4 signals into OTU3 frames

    40G OTN Framing

    • Provides programmable PM/TCMi Delay Measurement capability.
    • Flexible insertion and extraction of OTUk, ODUk, and OPUk overhead byte information.
    • Inserts OTUk SM, GCC0, RES, ODUk RES, TCM ACT, FTFL, PM, EXP, GCC1, GCC2, and APS/PCC overhead through internal register control or an external overhead port.
    • Supports GMP payload mapping with external justification control.
    • Optionally inserts ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals.
    • Interprets and extracts OUT SM, GCC0, RES, ODU RES, TCM ACT, TCM (support for up to 6 levels of tandem connection monitoring), PM, EXP, GCC1, GCC2, and APS/PCC overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.


    • OTN Transponder
    • OTN Subsystem
    • Line cards
    • Test equipment