XS800 100G OTN Transponder

General Description

The Xelic 100G Optical Transport Network (OTN) Transponder provides the flexible transport of signals through a configurable highly integrated subsystem. Client signals supported include 100GE and OTU4 rates with line side ODU4/OTU4 signals configurable through internal register control. The subsystem contains independent 100G OTN Framer, OTL4.10, 100GE, and GFEC core processors with configurable options and a comprehensive programmable feature set. Independent interfaces are provided for framer GMP payload insertion/extraction control and external overhead port insertion/extraction. Optional loopbacks bypass modes, counters, and programmable consequential actions are available for debug and system integration purposes. A flexible 640-bit architecture is implemented with a data valid scheme and a high speed system clock operating at a rate up to 185MHz. The 100G Optical Transport Network (OTN) Transponder subsystem is targeted for both ASIC and FPGA applications.



    • Implements 16-bit register interface for programming of internal registers.
    • Complies with IEEE 802.3ba, ITU-T G.709 and ITU-T G.798 specifications.

    100G Ethernet Processing

    • Provides alignment of incoming PCS blocks for all ten incoming lanes.
    • Optionally generates link fault indication for signal fault detection.
    • Contains optional PCS descrambling/scrambling functions.
    • Performs lane marker alignment and deskew.
    • Includes performance counters and maskable interrupts for PCS sync errors (BER), PCS Block errors, and lane marker PCS BIP3 error detection and adjustment capability.

    100G GFEC

    • Contains 7 parity overhead
    • Encoder includes single bit error insertion for diagnostic purposes.
    • Provides outputs for scrambled line values of corrected ones and corrected zeroes
    • Provides corrected symbols and uncorrected codewords outputs.
    • Provides a configurable High BER alarm.


    • Provides optional OTUk AIS insertion.
    • Supports OTU4 lane rotation for OTL4.10 multichannel parallel interfacing.
    • Detects FAS OOF/OOM and LOF/LOL conditions with optional interrupt generation.
    • Detects OTL AIS and OTUk-AIS error condition with optional interrupt generation.
    • Supports Alignment and deskew of incoming lane data.
    • Provides inverse multiplexing (lane rotation) of incoming OTL4.10 signals into OTU4 frames

    100G OTN Framing

    • Provides programmable PM/TCMi Delay Measurement capability.
    • Flexible insertion and extraction of OTUk, ODUk, and OPUk overhead byte information.
    • Inserts OTUk SM, GCC0, RES, ODUk RES, TCM ACT, FTFL, PM, EXP, GCC1, GCC2, and APS/PCC overhead through internal register control or an external overhead port.
    • Supports GMP payload mapping with external justification control.
    • Optionally inserts ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals.
    • Interprets and extracts OUT SM, GCC0, RES, ODU RES, TCM ACT, TCM (support for up to 6 levels of tandem connection monitoring), PM, EXP, GCC1, GCC2, and APS/PCC overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.


    • OTN Transponder
    • OTN Subsystem
    • Line cards
    • Test equipment